Focused ion beam (FIB) etching has been widely used as a versatile maskless lithography technique in numerous fields. Nano-patterning using FIB etching is generally employed in order to develop or locally modify devices, including integrated circuits, micro-systems and micro-photonics. Due to the ability of FIB patterning to save time and process steps, it can be exploited to develop prototypes of both electrical and optical devices: Many photonic and optoelectronic devices employ sub-wavelength-scale structures, such as diffraction gratings, Distributed Bragg reflectors (DBRs), photonic crystals, and surface plasmon devices.
In semiconductors commonly used in microelectronics and integrated photonics, high aspect ratio nanoscale milling cannot be achieved due to the material decomposition (see FIG. 1a and explanation hereinafter) caused by the beam-tail ion local energy injection and thus deep FIB milling in semiconductors was reported only for large feature sizes of more than 0.15 μm. The aspect ratios achieved for bare semiconductor material nanoscale milling is usually lower than 3.
Such low aspect ratio semiconductor milling may cause unwanted metal cuts or short circuits in microelectronics FIB circuit editing (see FIG. 2(a)).
In photonic devices with features as small as few tens of nanometers needed for short-wavelength (visible and UV) applications such low aspect ratios prevent the fabrication of efficient periodic structures.
In methods of microelectronics circuit editing by FIB milling known in the art, the low aspect ratio problem is usually prevented by a Design for Testing (DFT) methodology in which the designer determines in advance the critical signals to be potentially edited by FIB. However, this method wastes time and crucial chip area and, only the predetermined signals can be accessed.
In micro-photonics, alternative multi-step electron-beam lithography followed by chemical etching techniques must be used instead of FIB for nano-scale features which take up much more time and resources.
U.S. Pat. No. 5,580,419; entitled “Process of making semiconductor device using focused, ion beam for resistless in situ etching, deposition, and nucleation”; to Berenz, John J.; disclose a method for producing ultra dense and ultra fast integrated circuits utilizing an advanced ion beam processing system.
U.S. Pat. No. 5,043,290; entitled “Process for forming electrodes for semiconductor devices by focused ion beam technology”; to Nishioka, Tadashi; et at.; discloses a method for forming an insulator-covered electrode on semiconductor substrate by forming a conductor layer on insulation film, exposing part of substrate, and forming terminal connection electrode.
U.S. Pat. No. 6,297,503; entitled “Method of detecting semiconductor defects”; to Bindell, Jeffrey B.; et at.; discloses a defects detection method for semiconductor devices, involving scanning thin layer specimen surface with electron beam using scanning electron microscope, with lateral resolution of about electron beam size.
U.S. Pat. No. 6,252,228; entitled “Method of analyzing morphology of bulk defect and surface defect on semiconductor wafer”; to Cho, Sung-hoon; et at.; discloses a bulk defect analysis method for semiconductor wafer, involving analyzing bulk defect in wafer using specimen which is manufactured by milling wafer by preset marker formed at position near bulk defect existence area.
U.S. Pat. No. 6,545,490; entitled “Trench-filled probe point for a semiconductor device”; to Bruce, Victoria J.; discloses a semiconductor package manufacturing and testing method e.g. for flip-chip circuit package, involving filling conductive material in trench that is formed in back side of package, in order to provide probe point.